Problem with IORD and IOWR instructions

Are you sure that your delay is enough to guarantee that the first CPU has written the data before the second one reads it? How do you program the two CPUs?

Alternatively you could have the second CPU wait in a loop until it reads 9 from the shared memory and see if it ever gets out of the loop.

For the timing requirements, have a look at the critical warnings in Quartus. If you have a "Timing requirements not met" critical warning then you have a timing problem that could lead to all kinds of bugs.