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Altera_Forum's avatar
Altera_Forum
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13 years ago

Problem with IORD and IOWR instructions

Dear all, I have a qsys system composed of two NIOS that can access a shared memory (data masters are connected to the memory), when I use the instructions IORD and IOWR I don't obtain the r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Are you sure that the address is correct?

You can put Signaltap probes on the shared memory's Avalon interface and monitor what the CPUs are doing when trying to access it.