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Altera_Forum
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13 years ago

Problem with burstcount > 2 for Avalon MM Master to SDRAM

Hello, I am trying to implement a burst transcation with SDRAM using Avalon MM Interface. The following Verilog code works fine for burstcount = 2: module hw_det_3by3( clk, re...
Altera_Forum's avatar
Altera_Forum
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12 years ago

I would just simulate your design so that you can view everything to perform proper debug.

Although I'm not sure why the status bit does not assert, I think you want your count register to be two bits wide otherwise you will end up overriding the value in minor10 due to count register rolling over.