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Honored Contributor
Honored ContributorProblem with burstcount > 2 for Avalon MM Master to SDRAM
Hello, I am trying to implement a burst transcation with SDRAM using Avalon MM Interface. The following Verilog code works fine for burstcount = 2: module hw_det_3by3(
clk,
re...
Altera_ForumHonored Contributor
Honored Contributor> Is there also a tool to monitor SDRAM content at runtime?
You could make an Avalon master that reads an address. Connect both that and your other stuff to the memory - Qsys will take care of adding arbitration. Or get your "test" master to read through a range of address and monitor the results with SignalTap. Mark.
