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Altera_Forum
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13 years ago

Problem with burstcount > 2 for Avalon MM Master to SDRAM

Hello, I am trying to implement a burst transcation with SDRAM using Avalon MM Interface. The following Verilog code works fine for burstcount = 2: module hw_det_3by3( clk, re...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Many thanks for the tip, this already helped me to identify several mistakes.

Is there also a tool to monitor SDRAM content at runtime?

Had a look at In-System Memory Content Editor, but seems like it only supports on-chip memory... (I am using the SDRAM Controller Component in Quartus).