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Altera_Forum
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13 years ago

Problem with burstcount > 2 for Avalon MM Master to SDRAM

Hello, I am trying to implement a burst transcation with SDRAM using Avalon MM Interface. The following Verilog code works fine for burstcount = 2: module hw_det_3by3( clk, re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

> Also, is there are a possibility I can monitor my signals (avm_sdram_writerequest, avm_sdram_readdatavalid etc.) during runtime?

Hi,

Have a look at the signal tap logic analyzer included in Quartus. Very useful for tracking down this kind of thing and it will allow you to see the signals in action and trigger on their state.

Mark.