Problem with Altera timing model for LAN91C111?

The fix for this went out with either 5.0 or 5.0SP1 -- get 5.0SP1 and you're sure to have it. To apply this to an existing system you'll need to open SOPC Builder, remove the ethernet component, and then add it back in before generating. The example designs that ship with 5.0SP1 should have this modification built in and not need any alteration.

We analyzed the timing presented in the SMSC literature as well as the actual behavior of the ARDY output and decided that the most efficient solution (as well as best performing) was simply to ignore ARDY and treat every transfer to/from the lan chip as if ARDY asserted for its maximum time, as specified in the SMSC datasheet.

Why was this done, you may ask? Simple: In hardware testing we found that ARDY was negated by the ethernet chip on every transfer to/from it -- therefore, modifying wait-state values to pretend that ARDY was negated for the maximum amount of time results in meeting chip timing withuot any additional avalon logic or complexity to worry about getting just right.