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Altera_Forum's avatar
Altera_Forum
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19 years ago

Problem with a pll

i have a new prototype of my own board with a 2c20-8 inside, at 49Mhz. testing the sdram, i found the pll lose cycles, and the clock signal to the sdram is erroneus (the high time is double than t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

We had a lot problems with cyclone chips access to SRAM. As far as we tested the problem was with bad power supply decoupling. Check Altera provided recommendations.

Switching a lot of pins from 1 to 0 sinks a lot of current from capacitive loads on pins, causing quality deterioration of the in-chip ground (crashing the processor in our case).

We did not have any problems with Cyclone I chips, so it seems that Cyclone II are much more prone to such problems.

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