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Altera_Forum
Honored Contributor
12 years agoProblem Running Nios II Design Standalone
Normally I use HDL for everything, but I’m trying to move into soft processor and SoC design. I created a Quartus/Qsys project to run the Nios II Binary Count example code project on a DE0-Nano devel...
Altera_Forum
Honored Contributor
12 years agoNote that you can put the JTAG UART back in the QSys project and just set stdout/stderr to none in the BSP settings. That way if you ever need to debug your project, you just need to change the bsp settings and don't need to recompile the QSys and Quartus projects.