Problem in using Avalon_Tristate_slave...

Hello,

I am currently using " Altera Stratix 1S10 Development Kit".

In SOPC Builder, I wanted to connect my User Logic to Nios Processor through Avalon_Tristate_slave.

The Entity Interface in VHDL code of my User logic [Inverter]is:

entity pipeline is

Port ( clk : in std_logic;

reset : in std_logic;

cs : in std_logic; -- chipselect

wr : in std_logic; -- write

rd : in std_logic; -- read

Outen : in std_logic; -- outputenable

dio : inout std_logic_vector(31 downto 0)); -- Data Bidirectional

end pipeline;

Here, I tried to add this New Component in SOPC builder.

While editing the componet by "Component Editor" wizard, I have chosen Avalon_tristate_slave_0 in Interface-Tab.

Then in Signals Tab, Signal type option for this bidirection signal: " dio" is not indicating the type "Data". So by this, the Component is NOT Set as "OK" by Editor. So I am unable to proceed.

I have gone through the document "mnl_avalon_spec.pdf", there I found this is the minimum requirement of signals to be done, for Tristate Bus Interface.

Then What would be the problem, Can anyone help me out??

Regards,

K V Naresh