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Altera_Forum's avatar
Altera_Forum
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13 years ago

Problem in getting final output.

hello.... I am trying to build custom peripheral using NIOS II processor on DE 2 board. My application is edge detection of the image using sobel operator. I am using C code for transmitti...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Those critical warnings don't come from your code. For (1) and (2), you need to provide a sdc file with all your timing constraints, to be sure the compiled design meet your timing requirements.

For (3) you need to assign FPGA pins to your signals, using the pin planner.