Honored Contributorproblem in designing custom peripheral
I designe a custom peripheral including a slave port with variable latency.So Its avalon interface signals is following:
clk,reset_n,ic_addr,ic_be_n,ic_cs,ic_data,ic_rd_n, ic_wr_n,ci_data,ci_valid,ci_wa
itrequest.
Signal ci_valid is used to inform nios2 of coming of valid read-data.Then I created a simple system to test the component but I get trouble .The signal ci_valid seems be ignored by System Generator Program because it is not wired to any other modules generated by Sopc Builder while both ci_data and ci_waitrequest is wired to a module named "custom_component_0_avalon_slave_0_arbitrator" . I think signal ci_valid should also be wired to that module but it is not.Why? What might I omit? help me~~~
custom peripheral name:custom_component
custom_component_0 is a instance and relative PTF section contained in system PTF file is as follows:
MODULE custom_component_0
{
class = "custom_component";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
PORT_WIRING
{
}
SIMULATION
{
DISPLAY
{
SIGNAL x101
{
name = "custom_comp_hou/avalon_slave_0";
format = "Divider";
}
SIGNAL x102
{
name = "ic_addr";
radix = "hexadecimal";
}
SIGNAL x103
{
name = "ic_be_n";
}
SIGNAL x104
{
name = "ic_cs";
}
SIGNAL x105
{
name = "ic_data";
radix = "hexadecimal";
}
SIGNAL x106
{
name = "ic_rd_n";
}
SIGNAL x107
{
name = "ic_wr_n";
}
SIGNAL x108
{
name = "clk";
}
SIGNAL x109
{
name = "reset_n";
}
SIGNAL x110
{
name = "ac_ACK_addr";
}
SIGNAL x111
{
name = "ac_ACK_data";
}
SIGNAL x112
{
name = "sc_sa_tag_in";
radix = "hexadecimal";
}
SIGNAL x113
{
name = "sc_data";
radix = "hexadecimal";
}
SIGNAL x114
{
name = "ci_data";
radix = "hexadecimal";
}
SIGNAL x115
{
name = "ci_valid";
}
SIGNAL x116
{
name = "ci_waitrequest";
}
SIGNAL x117
{
name = "cs_addr";
radix = "hexadecimal";
}
SIGNAL x118
{
name = "cs_be_n";
}
SIGNAL x119
{
name = "cs_data";
radix = "hexadecimal";
}
SIGNAL x120
{
name = "cs_rd_n";
}
SIGNAL x121
{
name = "cs_wr_n";
}
SIGNAL x122
{
name = "cs_tag";
radix = "hexadecimal";
}
SIGNAL x123
{
name = "ca_empty";
}
SIGNAL x124
{
name = "ca_wr_n";
}
}
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Width = "26";
Address_Alignment = "dynamic";
Data_Width = "8";
Has_Base_Address = "1";
Has_IRQ = "0";
Setup_Time = "0";
Hold_Time = "0";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Read_Latency = "0";
Max_Pending_Read_Transactions = "2";
Is_Printable_Device = "0";
Is_Memory_Device = "1";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Base_Address = "0x00000000";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
PORT_WIRING
{
PORT ic_addr
{
width = "26";
width_expression = "";
direction = "input";
type = "address";
}
PORT ic_be_n
{
width = "1";
width_expression = "";
direction = "input";
type = "byteenable_n";
}
PORT ic_cs
{
width = "1";
width_expression = "";
direction = "input";
type = "chipselect";
}
PORT ic_data
{
width = "8";
width_expression = "";
direction = "input";
type = "writedata";
}
PORT ic_rd_n
{
width = "1";
width_expression = "";
direction = "input";
type = "read_n";
}
PORT ic_wr_n
{
width = "1";
width_expression = "";
direction = "input";
type = "write_n";
}
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
}
PORT reset_n
{
width = "1";
width_expression = "";
direction = "input";
type = "reset_n";
}
PORT ac_ACK_addr
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT ac_ACK_data
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT sc_sa_tag_in
{
width = "2";
width_expression = "";
direction = "input";
type = "export";
}
PORT sc_data
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT ci_data
{
width = "8";
width_expression = "";
direction = "output";
type = "readdata";
}
PORT ci_valid
{
width = "1";
width_expression = "";
direction = "output";
type = "readdatavalid";
}
PORT ci_waitrequest
{
width = "1";
width_expression = "";
direction = "output";
type = "waitrequest";
}
PORT cs_addr
{
width = "26";
width_expression = "";
direction = "output";
type = "export";
}
PORT cs_be_n
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
}
PORT cs_data
{
width = "8";
width_expression = "";
direction = "output";
type = "export";
}
PORT cs_rd_n
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
}
PORT cs_wr_n
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
}
PORT cs_tag
{
width = "2";
width_expression = "";
direction = "output";
type = "export";
}
PORT ca_empty
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
}
PORT ca_wr_n
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
}
}
COMPONENT_BUILDER
{
AVS_SETTINGS
{
Setup_Value = "0";
Read_Wait_Value = "1";
Write_Wait_Value = "1";
Hold_Value = "0";
Timing_Units = "cycles";
Read_Latency_Value = "0";
Max_Pending_Read_Transactions_Value = "2";
Address_Alignment = "dynamic";
Is_Printable_Device = "0";
Is_Memory_Device = "1";
external_wait = "1";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
hdl_parameters
{
flag_tag = "2'b00";
}
}
HDL_INFO
{
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/custom_component.v,
__PROJECT_DIRECTORY__/custom_component_0.v";
}
}
}
