Problem debugging on a custom cyclone board

vlorenzo (http://www.alteraforum.com/forum/member.php?u=21131) http://www.alteraforum.com/forum//proweb/statusicon/user_offline.gif

Altera Scholar

Hi VLorenzo,

I have the same problem. I try to set -72ns, but it's still doesn't work. I see that you got it work with SDRAM PLL phase delay. Could you show me how to set it up or could you post the setting in SOPC of PLL?

Thanks,

Sean