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Honored ContributorProblem debugging on a custom cyclone board
Hi: This is just about getting us crazy. We have designed a custom board with a Cyclone chip for implementing a NIOS II processor, both the processor and the SDRAM seem to work ok (some impleme...
Altera_ForumHonored Contributor
Honored Contributorvlorenzo (http://www.alteraforum.com/forum/member.php?u=21131) http://www.alteraforum.com/forum//proweb/statusicon/user_offline.gif
Altera Scholar Hi VLorenzo, I have the same problem. I try to set -72ns, but it's still doesn't work. I see that you got it work with SDRAM PLL phase delay. Could you show me how to set it up or could you post the setting in SOPC of PLL? Thanks, Sean
