Problem debugging on a custom cyclone board

Just for others to note:

The reason SDRAM access worked with GERMS is that subtle memory timing problems will not reveal themselves as a result of the CPU data master accessing RAM -- the data master performs one read or write every once in a while, but not continuously. By contrast, instruction fetch (and cache fills) will exercise the SDRAM interface with a new word of data on each clock. If there is a subtle timing problem, such as setup/hold violations due to clock-phase-shifts, then these will be manifested when you try to run code from SDRAM, or do something like a DMA transfer.