principle of acquisition f=10MHz signal with nios software

I don't know how to use nios vga controller. But I read in a book how to make it. Resolution 640 x 480 8 bit color depth. It uses a 512K SRAM ( as frame buffer ) because timing scheme it's easier than SDRAM.

The fpga has a 50 MHz clock, so a pixel tick slow down to 25 MHz. Also, this pixel tick switch the address of the memory between the cpu and the vga controller. So, it's like a dual port access. But multiplexed in time. A state machine place the read and write signal of the cpu in the proper clock cycles.