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Altera_Forum
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20 years ago

Potential _interrupt_handler infinite loop

I added a 16550 UART FPGA Core and when receiving large quantities of data my system is locking up because it is in an infinite loop within the _interrupt_handler assembly code in vector.s. What I f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

The UART Core was designed with level interrupts, but unfortunately there was a bug in the Timeout Interrupt where it was deasserted when the next data byte was received instead of when SW read the UART. Changing this eliminated the problem. Thanks for the help and pointers.

Does anybody have any comments on whether or not the _interrupt_handler code should be changed to prevent an infinite loop?

Thanks,

Stefan