Posible Problem with ISR Edge PIO

It is in fact how the hardware peripheral response to a read operation on its slave interface. I don't think you can do in software.

In Verilog HDL it should look like this :

reg LatchedInput;
reg InputEdge;
assign IrqStatus = IrqEnable & InputEdge;
always @*
  case (Address)
    ...
    `IRQ_STATUS : Dout = IrqStatus;  // read out the interrupt status 
    ...
  endcase
always @(posedge Clk or posedge Reset)
  if (Reset)
    begin
      InputEdge <= 0;
      LatchedInput <= 0;
    end
  else
    begin
      LatchedInput <= Input;
    
      // this resets the input edge capture when reading the interrupt status
      if (!nRd && Address == `IRQ_STATUS)
        InputEdge <= 0;
      //this sets the capture register, with higher priority than resetting
      //when a new edge occurs just at reading the irq status, it will generate e new interrupt
      if (Input && !LatchedInput)
        InputEdge <= 1;
    end

Maybe there is a software trick for it like disabling interrupts, changing order of commands, ... I'm not an "Altera PIO component"-specialist, I usually roll my own.

For the edge capture, I don't think the miss of an edge is so critical, what happens if a new edge comes in when the older is not processed yet? It is lost anyway. For this you need a counter to remeber how much edges occured.