Porting PIO C-code from ARM-7 to Nios II (SE1-board) + performance issue.

Each call to the pio function results in 2 for loops that call the delay function 16 times which loops 6000 times. Each call therefore delays 32 times decrements 6000 times.

Actually I think they are embedded in a for that loops 4 times.

The delay which simply decrements wait is really the only thing consuming cpu time. So the comparison is really showing how fast the different cpu's/programs can:

load 1;

load wait;

subtract;

store wait - 1;

load 0;

compare wait - 1, 0;

if (true) return;

else

jump to load 1;

Question 1: Did the compiler allocate registers or memory for the operands?

Question 2: Is this loop sufficient to measure cpu performance? In other words, is it a good

benchmark of cpu performance?