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Hi,
I was able to make it running.
I have made no changes to NIOS code except changing this define:
#define IO_data 4
Also in the code the DM9000A.C file was included, which is rather bad so I only included .h file
and had to move ether_addr table to .C file from .h.
In my DM9000A component i have changed iDATA and oDATA to 32 bit and simply assigned
lower 16 bits to ENET_DATA.
I also resized iCMD to 8 bits and found out that bit 4 goes up when I write.
So i simply assigned this bit to ENET_CMD.
Also I changed read wait and write wait to 3 clock cycles in my DM9000A component (it's related to 100MHz clock for NIOS).
Best,
madness
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Is it true that regardless of the actual PHY chip, the mdio interface is common, and the device specific initialization is done in software?
If so, couldn't an existing built-in qsys component (ex. LAN91C111) be instantiated, but registers initialized for the DM9000A?
EDIT: Since these chips have MACs built-in to them, why is another MAC (Altera's TSE) added into the system design... how does that even work?
Honored Contributor
