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Altera_Forum
Honored Contributor
19 years agoPolling & INTs with NIOS II
Hi, I have 2 cascaded processors with a shared memory. The first processor writes its data in the shared memory and when it finishes, the second processor must be notified that the data is availab...
Altera_Forum
Honored Contributor
19 years agoThanks a lot !!!
I am trying it now but I want to make sure of my connections. I am pipelining 2 processors having a shared memory and cpu2 starts code execution when PIO1 is raised to logic'1'. I defined a timer for each processor, made the mutex and the on-chip memory acting as a message buffer RAM (as the multiprocessor tutorial says). Then I made the PIOs: PIO1 as output (1-bit) and connected to the data master of cpu1 and cpu2. PIO2 as input (1-bit) and connected to the data master of cpu2 Are these connections right ? especially the last one ? I want to make cpu1 put logic '1' in PIO1 when it finishes its part, and then PIO1 affects PIO2 which INTs cpu2 to begin its code. Is this way right ? Thanks