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Altera_Forum
Honored Contributor
20 years agoPerformance Issues
I am in the process of debugging a custom Nios II system. I have implemented a NIOS II/f CPU with and EPCS controller. I have created a custom component to access a SRAM in which my firmware is runni...
Altera_Forum
Honored Contributor
20 years agoUnfortunately you are.
all of these profibuschips have both memory and registers with a single chipselect. the data to and from the profibus is stored inside the chip so this chip-memory area must be a memory inside the nios datamaster that the software can use 8/16/32 Bit access and even memcopy(move) operations without takeing care about that this device is a 8 bit device. (all available softwarestacks need this and we do not want to re-write such an stack an certify it) on the other hand with the same chipselect you gain access to the registers and some of them monitor a read access, so if you want to read a 8 bit register, but executed is 4 read cycles, then you do in real life a read from 3 registers that are not accessed by the software. the crazy thing is that the byteenables indicate which byte is requested. so the only workaround is to insert a statemachine between avalon and the profibuschip that fetches only these byte that are requested by the software. this works fine here. so for the software it is neccesary to have a memory modul instead of a register modul to get rid of the gaps in the memory. but no additional (wasted) read cycles.