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Altera_Forum
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20 years ago

Performance Issues

I am in the process of debugging a custom Nios II system. I have implemented a NIOS II/f CPU with and EPCS controller. I have created a custom component to access a SRAM in which my firmware is runni...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Thank you everyone for all your information.

MSchmitt, when you stated :-

"nowadays the readdata is a wire with a set of combinatorical logic and now each access is only 1 clock cycle long, regardless of read or write."

what did you mean ?