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Altera_Forum's avatar
Altera_Forum
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20 years ago

Performance Issues

I am in the process of debugging a custom Nios II system. I have implemented a NIOS II/f CPU with and EPCS controller. I have created a custom component to access a SRAM in which my firmware is runni...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Two things come to mind that might be the reason for the double reads. The first is whether or not you are running the debugger. The debugger will access the memory. Second, if you are not running the debugger are you looking at the address appropriately? Does the processor have access to 16 bits of data on your SRAM? It may be doing byte reads, first byte in first read and second in second read.

Verify your SRAM setup in SOPC Builder and be sure it matches your part in terms of size and latency.

Good luck.