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Altera_Forum's avatar
Altera_Forum
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20 years ago

performance degradation

We are running heterogeneous multiprocessor NIOS2 cores on out Stratix2 fpga. We have made a benchmark that contends for a shared memory locked by a hardware mutex, performs a multiply-accumulate, an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

difficult question to answer without a more detailed memory layout...

- are the different CPUs sharing the same memory also for code and data?

- what kind of code is executing on each CPU?

- are you using GP-relative addressing or not? this changes the frequency of memory accesses

- what about caches?

bye

PJ