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Honored Contributor
Honored ContributorPCIe RootPort+EndPoint Simulation
I have designed two systems - a RootPort and an EndPoint on two different PCBs, each with a NIOS II. Now, I am trying to do system-level simulation with both designs in one testbench. My Endpoint ...
Altera_ForumHonored Contributor
Honored ContributorWhen you generate the SOC in QSYS you can add a BFM master. When you synthesize the SOC the BFM drops out. If you have a NIOS II you can hold it in reset by using a "force" command in you testbench. This is so it does not interfere with your simulation.
