PCIe Root Port Configuration using NIOS via Avalon-MM Interface on Cyclone 5 Board

Have you found any reference?

Thanks.

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Does anyone have refence code or steps needed for configuring PCIe (PCI Express) as Root Port (Root Complex) via the NIOS-II processor on

a Cyclone 5 board using the Avalon-MM interface ?

I'm trying to understand the basic steps needed to configure the PCIe interface and leverage a reference example for our application.

Any specifics regarding root port and end port registers and there values would also be helpful. Once again, I'm trying to configure the

PCIe interface using the NIOS-II/f proccessor via the Avalon-MM interface and expecting everything to be memory mapped addressed and

would like feedback on this as well.

Thanks

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