PCIe Root Port Configuration using NIOS via Avalon-MM Interface on Cyclone 5 Board

Have you found any reference?

Thanks.

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Does anyone have refence code or steps needed for configuring PCIe (PCI Express) as Root Port (Root Complex) via the NIOS-II processor on

a Cyclone 5 board using the Avalon-MM interface ?

I'm trying to understand the basic steps needed to configure the PCIe interface and leverage a reference example for our application.

Any specifics regarding root port and end port registers and there values would also be helpful. Once again, I'm trying to configure the

PCIe interface using the NIOS-II/f proccessor via the Avalon-MM interface and expecting everything to be memory mapped addressed and

would like feedback on this as well.

Thanks

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I did not find any reference code to get our system up and running and therefore had to write my own PCIe interface driver which interfaces to the CRA Slave and to generate TLP config packets. Our board contains a Cyclone 5 configured as a root port which communicates over PCIe to a TI C6655 DSP as an endpoint. NOTE: The Altera C5 Users guide for the bit definitions for the SOP and EOP bits is not correct.....The users guide has them opposite of what they truly are. Table 8-32 on page 8-17 is incorrect..... SOP is really Bit 0 while EOP is really Bit 1...

Hope this helps

Ok thank you for the hints.

Michele.

Could you give me NIOS basic functions to access CRA slave, please.

Thank you