PCIe Root Port Configuration using NIOS via Avalon-MM Interface on Cyclone 5 Board

I did not find any reference code to get our system up and running and therefore had to write my own PCIe interface driver which interfaces to the CRA Slave and to generate TLP config packets. Our board contains a Cyclone 5 configured as a root port which communicates over PCIe to a TI C6655 DSP as an endpoint. NOTE: The Altera C5 Users guide for the bit definitions for the SOP and EOP bits is not correct.....The users guide has them opposite of what they truly are. Table 8-32 on page 8-17 is incorrect..... SOP is really Bit 0 while EOP is really Bit 1...