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Honored Contributor
Honored ContributorPCIe Memory Write/Read abnormal behavior
We have a PCIe core that is configured as a rootport. It is connected to a switch which has a single device on the downstream side. We enumurated the PCIe busses successfuly and moved on t...
Altera_ForumHonored Contributor
Honored ContributorFound the problem ! The TX packet has two extra DW of 0x00000000 which must not be there. This violates the memory write spec. for 32bit access. So, instead
of: TX Data = 0x40000001 TX Data = 0x00001f0f TX Data = 0x40000100 TX Data = 0x00000000 TX Data = 0x123abcde TX Data = 0x00000000 it should be: TX Data = 0x40000001 TX Data = 0x00001f0f TX Data = 0x40000100 TX Data = 0x123abcde The SW guy has a red face now... S. (HW guy)
