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3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    I believe the opencores 2.0 core is intended for ASIC implementation; it is impossible to achieve 480Mbps on Cyclone FPGAs; they don't have the appropriate transceivers.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    OK, tnx. But that's out of the question right now.

    I would like to know how to initialize the core, open an endpoint, handling interrupts, transmitting/receiving data, etc.