Hi,
I am also trying to modify the Wishbone Ethernet IP core to be implemented in Quartus and SOPC Builder. I have run the verilog codes in the "rtl\verilog" folder in Quartus and it runs without any errors and warnings.
I was advised before this to modify the eth_wishbone.v file by dropping the wishbone bus interface and adding the avalon bus interface.
While I was studying this file, I saw that some part of it did support Avalon, such as the code:
`ifdef ETH_AVALON_BUS
..........
endif
And also I tried to identify the various Wishbone signals for Wishbone common, Wishbone slave and Wishbone master, and finding the corresponding compatible signals in Avalon such as chipselect, waitrequest, byteenable, ....etc. While I did take out some seems unused signals by Avalon such as those error signals : err_<>_ and m_wb_cti_o and m_wb_bte_o. And i also dropped off those with
`ifdef ETH_WISHBONE_B3
endif
I really not sure whether I am doing the correct way.
Then once the file is compiled without syntax errors(though, ..) , I tried to create a new component in SOPC Builder using Component Editors. Once the signals are loaded in the Signals Tab, I tried to set the signal types such as whether it is "avalon_slave" or " avalon_master" and whether it is a " chipselect" ,"begintransfer", "byteenable"...etc.
But there are some signals, I don't know whether it belongs to " avalon_slave " or "avalon_master" such as those going to and coming from PHY chip as follows:
(So I just see whether these signals is coming from PHY into a slave , so I put "avalon_slave" , "input" as "export" , or "global signals" as "export")
input InvalidSymbol; // Invalid symbol was received during reception in
//100 Mbps mode
input LatchedCrcError; // CRC error
input RxLateCollision; // Late collision occured while receiving frame
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
input DribbleNibble; // Extra nibble received
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input [15:0] RxLength; // Length of the incoming frame
input LoadRxStatus; // Rx status was loaded
input ReceivedPacketGood;// Received packet's length and CRC are good
input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
input r_RxFlow;
input r_PassAll;
input ReceivedPauseFrm;
// Tx Status signals
input [3:0] RetryCntLatched; // Latched Retry Counter
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts
//were made)
input LateCollLatched; // Late collision occured
input DeferLatched; // Defer indication (Frame was defered before
//sucessfully sent)
output RstDeferLatched;
input CarrierSenseLost; // Carrier Sense was lost during the frame
//transmission
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
input TxRetry; // Transmit packet retry
input TxAbort; // Transmit packet abort
input TxDone; // Transmission ended
output TxStartFrm; // Transmit packet start frame
output TxEndFrm; // Transmit packet end frame
output [7:0] TxData; // Transmit packet data byte
output TxUnderRun; // Transmit packet under-run
output PerPacketCrcEn; // Per packet crc enable
output PerPacketPad; // Per packet pading
// Rx
input MRxClk; // Receive clock (from PHY)
input [7:0] RxData; // Received data byte (from PHY)
input RxValid; //
input RxStartFrm; //
input RxEndFrm; //
input RxAbort; // This signal is set when address doesn't match.
output RxStatusWriteLatched_sync2;
//Register
input r_TxEn; // Transmit enable
input r_RxEn; // Receive enable
input [7:0] r_TxBDNum; // Transmit buffer descriptor number
// Interrupts
output TxB_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxE_IRQ;
output Busy_IRQ;
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
At first, I assign the wb_stb to avalon "chipselect" , and wb_cyc to avalon "begintransfer", and wb_sel to avalon "byteenable", after I have studied the Wishbone specs and Avalon specs, and assigned based on my understanding. But I came across a topic in this Forum, that Mr./Mrs. slava stated that " wb_stb" and "wb_cyc" can be tied together in the Verilog code file itself. So how to do or write the code of combining the wb_stb and wb_cyc to behave as avalon "chipselect".
Also, there is also a suggestion posted on using avalon naming :
avs_(avalon valid slave) and avm_(avalon valid master), so do I write these naming in the Verilog file, changing wishbone "m_wb_<signalname> " to "avm_<signalname>. How do these suggestions , come into play in my initial problem of implementing Ethernet IP core in Avalon SOPC?
I not sure whether I am doing the correct way, since I am still a new comer in Verilog and also Ethernet IP, therefore I need someone, some of you, who could kindly enlighten me. I really need help desperately.
Honored Contributor
