OnChip Memory - Addressing problem

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Are both of your CPUs and peripherals in the same SOPC Builder system?[/b]

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Yes, they are

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...per SOPC Builder system, you have an entire Avalon address space; no two peripherals can share that address space...[/b]

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Is it true even if each Cpu is the ONLY master of the onchip_memory?

         CPU1                                              CPU2
           |                                                      |
------------------                                 ------------------    
  |                   |                                 |                    |
JTAG1    MEMORY1                          JTAG2      MEMORY2
ONCHIP_MEMORY1: Base Address 0x00000000        Reset Adrress: 0x00000000        Exception Address: 0x00000020
ONCHIP_MEMORY2: Base Address 0x00000000        Reset Adrress: 0x00000000        Exception Address: 0x00000020
=> "cpu_1 and cpu_2: illegal reset address or exception address. All CPU reset or exception addresses must be unique"

This case should not be a problem.... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif there aren&#39;t shared peripherals....each CPU targets a unique memory!?!? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/dry.gif

In addition, in "AN 184: Simultaneous Multi-Mastering with the Avalon Bus" (page 3) I&#39;ve read:

...becasuse master and slave peripherals are connected with dedicated paths, multiple masters can be active at the same time and can simultaneously transfer data to theis slaves. this simoultaneous multi-master architecture offers great throughput performance advantages compared to a traditional, shared bus architecture. master peripherals do not have to wait to access a target slave peripheral, as long as another master does not access the same slave at the same time....

Please, help me...

Bye, Matteo