OnChip Memory - Addressing problem

Hi Matteo,

Can you clarify one point: Are both of your CPUs and peripherals in the same SOPC Builder system? That is, are you trying to put all that into SOPC Builder at once, or two you create two separate designs in SOPC Builder?

The reason I ask: per SOPC Builder system, you have an entire Avalon address space; no two peripherals can share that address space; so it is illegal to have two memories go from 0x1000-0x2000 (for example) even if they are mastered by two CPUs. On the other hand, if you create two separate systems (each with its own unique top-level system-name in SOPC Builder), this would be legal as you have two separate address spaces.

The Nios II IDE should allow this as well, since it looks at the Avalon address space corresponding to the PTF file (SOPC Builder system) that you provide during project creation... if this is not working please feel free to contact Altera support or send me a private message with your two PTF files and I'll investigate.

Some additional notes: If you are putting everything into a single SOPC Builder design and try to setup the addressnig as you are, you should be getting some error messages in SOPC Builder at the bottom of screen describing the addressing problem; this would normally prevent you from generating the HW for the design.

Second note: If you're creating two SOPC Builder designs in the same quartus design folder, I'd strongly reccomend naming all peripherals differently. Example: system1_cpu, system1_rom, system1_uart, system2_cpu, and so on... I think there is a known limitation regarding this because otherwise you'll get HW files generated on top of each other (with the same name).