on-chip memory

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originally posted by mendonca@Jul 24 2006, 11:19 AM

a hardware question: http://forum.niosforum.com/work2/style_emoticons/<#emo_dir#>/blink.gif

i&#39;d like to instantiate an on-chip memory just to store a char (8 bits) and a float variable (32 bits); so it&#39;ll demand 5 bytes. will i have problems in access to the float variable if i assign only 8 bits to the memory width --- in order to allocate exactly 5 bytes? is there any difference, about speed of access, when i use a diferent size to the memory width?

thanks.

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Think of the onchip memory being on a grid. There are rows and columns and each embedded memory block takes up a fixed amount of bits (whether you use them all or not). M4K blocks hava a "native" width of 36 bits wide and 128 rows (words). So if you want just 5 bytes you would end up only taking up 5/512 bytes of an M4K block. By selecting 8 or 32 bit width what you are doing is telling the tools how to subdivide each memory row. For example in the case of 8 bit memory think of the memory being 8 bits wide and having 512 rows. As you expand the memory width you loose rows (now Quartus II might do some optimizations to pack memory or achieve better timing but that&#39;s an advanced topic).

Check out page 2-2 in this document to see the difference between the three types of onchip memory and the width configurations they support (note if you target Cyclone/Cyclone II you only have M4k blocks in your device):

http://www.altera.com/literature/hb/stx2/stx2_sii52002.pdf (http://www.altera.com/literature/hb/stx2/stx2_sii52002.pdf)

With that said if you don&#39;t plan on storing any more than a 32 bit and an 8 bit value into a memory and you have around 50 LEs of logic available you might want to just create a custom component to store these values in registers. If you are not sure how to do that I recommend generating a system with a PIO and using the HDL file as a starting point to create your own logic. You would then feed your component HDL into "Component Editor" (see the following link for documentation on that):

http://www.altera.com/literature/hb/qts/qts_qii54005.pdf (http://www.altera.com/literature/hb/qts/qts_qii54005.pdf)

To answer your question about access time, the only time you&#39;ll see a slowdown is if you configure the memory to be 8 bits wide and start trying to read/write 32 bit values into it. Since it is 8 bits wide the Avalon switch fabric will perform four accesses to the memory. Now if you try to do an 8 bit access to a 32 bit memory then the Avalon switch fabric will handle it in a single cycle (minus the memory latency). Email me if you have further questions directed my way.