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Altera_Forum's avatar
Altera_Forum
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15 years ago

On-Chip Memory Required?

Hello all, I am new to NIOS, but quite familiar with FPGAs otherwise. I'd like to setup a NIOS II processor on a design that is already in place. I'd like to keep the on-chip memory usage to a bare minimum, and use off-chip storage for code. What is the best way to do this? I have a Cyclone III dev board with CFI flash, ddr, sram, etc, and I am trying to get the DDR to work as the codespace.

Do I necessarily NEED onchip ram? Or can it be replaced entirely with offchip? Ive been reading doc after doc about bootloaders and using an EPCS or CFI for bootloader, but they make little mention of where the code will be placed... A little insight would be great! Thank you.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The bootloader can be placed at any memory address location. Obviously for the sake of usability, it needs to be in non-volatile memory.

    As far as onchip memory usage. Even if you don't explicitly add onchip memory to your SoPC system, the processor does require some. Any cache you add to the CPU will use onchip memory. Aside from this the CPU will generally use RAM blocks for some pieces within the processor. Some of these might be inferred and you might be able to reduce it by telling Quartus to not infer RAM for these modules.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I understand the SOPC requirement for _some_ ram, for use as cache or registers, etc. But I would like to reserve most of the M9K blocks for other purposes, and it looks like on a EP3C25 I can only get about 32K before it is over utilized. And I just know the end code will need more space, considering the demo programs take 10-15k at least.

    So, its not a problem to store my fpgaconfig + code on the CFI or EPCS flash, and it will automatically copy the NIOS code to a DDR or other off-chip if I so choose? Good to know... now to just figure out how to get it to work!

    Any further insight will be highly regarded! Thank you!
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It's pretty darn easy. All you have to do is point the NIOS's boot address to your flash device. Then when you create your software BSP (board support package) you tell it you want to run everything out of your DDR. When you compile your project, it will automatically create the necessary bootloader and the resulting flash file (containing your code and the bootloader) that you just need to program into your flash device.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    One option is to write some demo programs that don't require ANY of libc. The first thing to go is any calls to printf(), then you need to get the calls to fclose() out of the wrapper that calls main().

    Having done that you have almost 0 byte of overhead, and it is possible to write programs that will load with 4k of code and data.

    A simple function to write strings to the jtag uart would be enough for daignostics.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    How do I get the fclose() out of the wrapper calling main?

    Thanks, Peter
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I removed the wrapper by renaming main() to (IIRC) _int_main().

    I think I then had to edit one of the source files.

    Another option would be to define the symbol!