On-Chip MEM contents (in user peripheral) access??

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originally posted by svhb@Jan 4 2006, 08:57 AM

do you mean : i have on chip memory connected to my cpu, and i want also read/write to it from external pins?

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On-Chip MEM is a part of user peripheral design, after geting the user peripheral design integrated, CPU wants to address the whole range of that On-Chip MEM.

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originally posted by svhb@Jan 4 2006, 09:46 AM

is this a verilog design, maybe if you post it (or parts from it, i can understand better the situation.

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Thanks a lot for Nios Expert svhb&#39;s help.

More detail about my problem will be:

I instantiated On-Chip MEM (LPM_MEM, two port, Block Type: AUTO) in a hardware design. Then I have to use CPU to access the data which is sitting on the LPM_MEM. Planning to use DMA to move data from custom logic to SDRAM or UART.

Currently I stuck at designing register file to let the LPM_MEM in the custom peripheral visible to Avalon bus. For general register accessing in custom peripheral I can simply use handcode. But my LPM_MEM is tens of thousand bytes large. So I guess there should be a smart way to solve.

I did think about using a single register to map the memory ouput port then use extra logic to play memory data byte by byte to the bus. (Definitely a stupid design.)

If the LPM address can be mapped to avalon bus just like SOPC builder assgined address. Accessing the whole LPM_MEM will be much more convenient.

Thanks a lot, I&#39;m still expecting help!

A possible way should be :

dual port memory connected with one port to the peripheral, and the peripheral connected as avalon slave. Bring the other memory port of the memory to outside this verilog module (address, data, read, write, ...). Connect this peripheral as register slave in SOPC builder.

Make a new peripheral in SOPC builder (choose legacy for simplicity), be sure to use &#39;memory slave&#39;. Choose the option &#39;export bus ports&#39; in the &#39;Instantiation&#39; page.

Connect the exported bus ports to the &#39;exported&#39; memory ports of the slave itself.

Now you can access the slave functionality with the register slave, that contains the functionality to handle one port of the dual port memory, and the cpu can reach the dual port memory with the memory slave mapped to an other address range. If you have a DMA master in the system, the memory can be accessed with DMA if it is set up correctly.

I did these kind of things in a previous project, and I hope this is an answer to your question.

Stefaan.

Spent a while studied svhb&#39;s suggestion. That&#39;s great, I think the key part of the solution is to use Legacy components.

I believe with svhb&#39;s help, I am getting closer.

Thanks a lot!