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Altera_Forum's avatar
Altera_Forum
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21 years ago

Not enough memory + ISS Problems?

OK, I have one or two problems. One, in our Nios 2 design, we have used all of the M4K memory blocks so we can't add in the JTAG debug module. This means I can't download code from t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

OK, maybe I'm not making myself clear. For my design, the final product will boot out of the EPCS. BUt, while I am developing the software, I obviously don't want to have to flash the EPCS everytime I make a change. All I want to do is run the code in RAM. Is there no way to do this?

For the Altera folks, exactly how do I need to setup my design so that I can use the debugger? Obviously I can't have an EPCS as the reset address. Nor can I have the SDRAM as the reset address. Where should the reset address be?