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ashutoshsriram's avatar
ashutoshsriram
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2 months ago

not able to use multiple niosV cores at the same time

when I run ultiple niosV cores at the same time im not able to acess each of them even though i am able to detect them , i am faced with  even though detecting gives me  and i am unable to ...
Embedded Applications Layer
Nios Architecture
Nios Cpu
ashutoshsriram's avatar
ashutoshsriram
Icon for New Contributor rankNew Contributor
2 months ago

That was the wrong qsys file the original qsys file had the reset port connected to the main clock reset only, was there any specific reason that you had to use the pio from niosv/m as a reset for the noisv/g? Can multiple softcores be connected in the same architecture? As connecting both nios through a reset bridge and normally to the clock reset didnt work and gave the same error.

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Hi All

     

    I would like to share that I have successfully tested version with Quartus 26.1, and it is working as expected.

    In my design, I have two NiosV instances instantiated in my design, and the Ashling IDE is able to detect and select either instance without any issues.

     

    Regards

    tehjingy