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ashutoshsriram's avatar
ashutoshsriram
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2 months ago

not able to use multiple niosV cores at the same time

when I run ultiple niosV cores at the same time im not able to acess each of them even though i am able to detect them , i am faced with  even though detecting gives me  and i am unable to ...
Embedded Applications Layer
Nios Architecture
Nios Cpu
ashutoshsriram's avatar
ashutoshsriram
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2 months ago

Thank you for your response. I had already tried that configuration as well. However, when I launch the Ashling debugger, it still reports that only 1 HART is available, even though both Nios V cores are visible in the JTAG scan chain and are detected correctly.

Because of this, I am unable to select or debug the second core. If there are any additional settings or requirements specific to multi-core Nios V systems that I may have missed, I would appreciate any suggestions.

  • knithink_Altera's avatar
    knithink_Altera
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    2 months ago

    Hi,

    There are no specific recommendations or methods for Nios V multi core design reset mechanism.

    Any working reset mechanism can be used.

     

    We have our Lockstep Example Design where we are using 2 Nios V cores.

    The Nios V/m core acts as the supervisor.

    The Nios V/g core has the Lockstep enabled.

    The design was released in 25.3.1. Following is the link for the same- https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.3.1/agf014ea-dev-devkit/niosv_g/lockstep 

    compiled design package- https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.3.1/agilex7_niosv_g_lockstep.zip 

    The Nios V/g core reset is connected to a PIO output. The PIO is driven by Nios V/m core. The Nios V/m core toggles the PIO value which resets the Nios V/g core.

    Nios V/m -> Write value 1 to PIO -> PIO output connected to Nios V/g reset input -> Nios V/g reset input is high which resets the core -> After some delay, write 0 to PIO via Nios V/m -> The reset input to Nios V/g goes low.

    The reset of the Nios V/m core is connected to the common reset signal that the remaining IPs are connected to. (The PLL locked output is used for the reset).

    May i know why uart1_niosv reset input is connected to 2 reset ports (reset bridge and debug reset output from other Nios V core)? The 2 resets may be conflicting and hence causing the core to remain in reset state. Is this specific requirement?

    If not, i suggest you just connect the reset to a single reset port.

    You can also explore the reset methodology in the above mentioned lockstep solution.