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ashutoshsriram's avatar
ashutoshsriram
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2 months ago

not able to use multiple niosV cores at the same time

when I run ultiple niosV cores at the same time im not able to acess each of them even though i am able to detect them , i am faced with  even though detecting gives me  and i am unable to ...
Embedded Applications Layer
Nios Architecture
Nios Cpu
knithink_Altera's avatar
knithink_Altera
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2 months ago

Hi,


Looking at the design snapshot shared by the user, it seems that one of the Nios V (uart1_niosv) reset signal is connected to 2 different reset interfaces.

One reset is coming from the reset bridge IP, which is the reset signal to most of the other IPs in the design.

On trying to correlate both snapshots, I think the other reset is coming from the debug module reset output of the second core (uart2_niosv).

Please confirm the same.

The other Nios V (uart2_niosv) has just one reset connection, which is correctly connected to the reset bridge.

 Assuming the reset is coming from debug module reset output of the second core:

  1. Please follow the description below to ensure debug reset output signal is triggered correctly.
  2. Also ensure that you are resetting the Nios V core with correct polarity.