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Elyouss's avatar
Elyouss
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3 years ago

Niosii PLL

Hello I'm a beginner in programming FPGA devices. I have to create several frequencies multiplier using PLL from an one Hertz input signal. With a nios processor I have to be able to make a program who let the user chose what PLL he want to use (if he want to multiply his signal by 2 he chose one PLL. If he want to multiply his signal by 3 he choose an another one). But I don't know how to begin since I never worked on Qsys. Is there some tutorials that I could follow to help me to finish my project ?

I'm using the Quartus II web edition and the Altera DE0 board. Thank you very much

8 Replies

  • ak6dn's avatar
    ak6dn
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Is this the DE0 board you have (from TerASIC)? The original DE0 board with the CycloneIII device?

    https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=364#contents

    You should download the support software from their site as it has several full demo applications.

    With respect to the PLL on that FPGA in particular, the minimum input frequency it requires is 5MHz.

    So if you really have a 1Hz input signal you need to think more on how it will interact with the PLL.

    • Elyouss's avatar
      Elyouss
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      3 years ago

      Thank you very much for your reply, that's the device on which I'm currently working. I already download everything I can from the terasic website haha. So, if the minimum input frequency is 5MHz and I have an 1 Hz input signal I can still finish my project or I will have to work with higher frequencies ?

  • ak6dn's avatar
    ak6dn
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Well it will be the case that you can't feed your 1Hz input signal into the hardware PLL on the FPGA and use it to multiply your frequency. So you have to find a different way to do it.

    But I might suggest it will rely on building a digital PLL state machine, oversampling your input 1Hz signal as the input, and generating an output signal that is 2X, 3X, 4X, etc of the input, based on user selection.

    • Elyouss's avatar
      Elyouss
      Icon for New Contributor rankNew Contributor
      3 years ago

      Got it thank you very much for your answer !

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    Agree with @ak6dn comments.


    However, I am curious to know why do you have such a low frequency input signal? You can use any crystal oscillator on the board of higher frequency which is within spec of FPGA PLLs and then use it to generate more frequencies internally.


    Regards


    • Elyouss's avatar
      Elyouss
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      because my project is to multiply the frequency from an external source and we are working on low frequencies. But yes, right now, I'm using the board's oscillator just to test my PLL in high frequency and to understand fully how to use Qsys. I want to connect the internal clock (pin G21) to one PLL and the PLL to the output pin R16 from the expansion header. But I haven't any signal when I test it on an oscilloscope. Do we have to program the nios processor with C to make an easy handling like that ?

      Best Regards

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    Yes, you need to program the FPGA with your NIOS II processor code.


    Regards