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Altera_Forum
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16 years ago

NiosII is slow? Or something I am doing wrong.

Hi all, I am playing with Cyclone II chip. It is custom board and there is ATMEGA16 running at 12MHz and FPGA with master clock 50MHz. FPGA is translating data from internal dualport memory ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It is very interesting post. Especially about FP comparisons.

For AVR I am using default settings and compiler from winavr package (http://winavr.sourceforge.net/) - no fancy libraries, no hand optimization.

Have you compiled Nios version with hardware floating code?

My compiled code size is about 2K bytes for nios.

Maybe Nios is not slow, but C compiller is bad? :)