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Altera_Forum's avatar
Altera_Forum
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16 years ago

NiosII is slow? Or something I am doing wrong.

Hi all, I am playing with Cyclone II chip. It is custom board and there is ATMEGA16 running at 12MHz and FPGA with master clock 50MHz. FPGA is translating data from internal dualport memory ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Another though I had is that you may want to verify your Nios code is actually using the FP hardware. I don't have any experience with this, but I have seen quite a few other posts on these forums about people having trouble with the compiler not actually using the FP hardware but using software emulation instead.

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It is very simple: software emulation of floating point will not fit to this Cyclone device's internal RAM. It is very small device and I must leave some dualport "video" RAM for LVDS data transfer.

And about optimization. I checked config, and it is -O2. Also, small C, no software floating point, no clean exit and etc. I need to strugle for each byte of RAM.