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Altera_Forum
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16 years ago

NiosII is slow? Or something I am doing wrong.

Hi all, I am playing with Cyclone II chip. It is custom board and there is ATMEGA16 running at 12MHz and FPGA with master clock 50MHz. FPGA is translating data from internal dualport memory ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I would expect this algorithm to be slow. This algorithm is performing many floating point calculations and without the floating point custom instruction all of that would end up being emulated in software using Nios II. The algorithm is also inherently slow as are most convergence algorithms and as a result you can speed it up by breaking down the algorithm and handling it in parallel (multi-core or hardware accelerators).

Why the performance is different between the two cores I'm not sure but make sure you are using the same compiler optimizations so that you are comparing apples to apples.