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Altera_Forum
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16 years ago

NiosII is slow? Or something I am doing wrong.

Hi all, I am playing with Cyclone II chip. It is custom board and there is ATMEGA16 running at 12MHz and FPGA with master clock 50MHz. FPGA is translating data from internal dualport memory ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Are you compiling everything with -O2 or -O3 ?

The default for the IDE is -O0, and that will generate atrocious code.

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I am using default configuration. I'll try to change these options.