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Altera_Forum's avatar
Altera_Forum
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15 years ago

NIOSII addressing for 32 bit wide SDRAM

Hello, first time poster here. As the title suggests, I have an FPGA accessing a 32 bit wide DDR2 device (actually 2x 16 bit devices with appropriately shared signals). Using SOPC builde...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

>>>>Timing is all met.

Or is it? <rhetorical>

Trimmed the system down to bare minimum and it worked.

Also, characterization showed unreasonable variability in the outcome.

I believe I have over-constrained the design and will work to properly constrain.