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Altera_Forum
Honored Contributor
15 years agoNIOSII addressing for 32 bit wide SDRAM
Hello, first time poster here. As the title suggests, I have an FPGA accessing a 32 bit wide DDR2 device (actually 2x 16 bit devices with appropriately shared signals). Using SOPC builde...
Altera_Forum
Honored Contributor
15 years agoSo, generating BE = 0xFF transactions from NIOS by using a DMA controller
by first transferring test data from NIOS to 64 bit onchipmem and then 64-bit DMA'ing this to the 64-bit local bus of the DDR2 controller and then reversing the process to get the data back to NIOS works fine. This creates an acceptable workaround for me. The whole BE = 0x0F/0xF0 thing not working properly is probably going to come down to the whole partial write support of the controller. Whatever. I have my solution and don't want to spend any more time thinking about this.