Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorNIOSII addressing for 32 bit wide SDRAM
Hello, first time poster here. As the title suggests, I have an FPGA accessing a 32 bit wide DDR2 device (actually 2x 16 bit devices with appropriately shared signals). Using SOPC builde...
Altera_ForumHonored Contributor
Honored ContributorA possible epiphany here...
w.r.t. my last few posts: I believe that accesses that involve 0x0F and 0xF0 BE(local_be) values would logically necessitate toggling the LSB of the mem column address but since the controller datasheet says the LSB of the mem column address is ignored for full rate that this is precisely why 0x0F and 0xF0 local_be are ignored thus the only way to see all the memory is to ONLY make 0xFF local_be accesses. Thoughts?
