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Altera_Forum
Honored Contributor
Honored ContributorNIOSII addressing for 32 bit wide SDRAM
Hello, first time poster here. As the title suggests, I have an FPGA accessing a 32 bit wide DDR2 device (actually 2x 16 bit devices with appropriately shared signals). Using SOPC builde...
Altera_ForumHonored Contributor
Honored ContributorHmmm, I wonder if accesses were made to be 64 bit on the local bus which means
that it would use local_be = 0xFF. I wonder if that would work. Perhaps using one of the DMA controllers. What's the easiest way to test this theory?
