Forum Discussion
Altera_Forum
Honored Contributor
15 years agoNIOSII addressing for 32 bit wide SDRAM
Hello, first time poster here. As the title suggests, I have an FPGA accessing a 32 bit wide DDR2 device (actually 2x 16 bit devices with appropriately shared signals). Using SOPC builde...
Altera_Forum
Honored Contributor
15 years agoThanks,
>>I would take a look at the Timequest documentation to learn the best practices. I have read through mountains of material and took the approx one hour online training and saw little practical value there. I found that the online training lacked examples of the nature "here is a violation and here is how we fix it and here is why we do it this way." Same thing with the TimeQuest docs. They seem to focus on "here are the tools and good luck." Hence the questions. :) >>Also for the SDRAM you have added it's automatically generated constraints to your >>Quartus project correct? That is correct. Actually, when I contacted support about failing constraints they made a couple of changes to the proj settings and gave me an additional.sdc file to further constrain the DDR which had a bunch of constraints like: set_max_delay -to [get_keepers *stage_counter\[*] 10.459 They have not solved my problems so I turn to the forum. Regards.